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-- Company: 
-- Engineer: Orson
-- 
-- Create Date:    19:09:38 12/09/2012 
-- Design Name: 
-- Module Name:    mul - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity mul is
    Port ( datain : in  STD_LOGIC_VECTOR (7 downto 0);
           multiplier : in  STD_LOGIC_VECTOR (1 downto 0);
           dataout : out  STD_LOGIC_VECTOR (7 downto 0));
end mul;

architecture Behavioral of mul is
	signal mul2 : std_logic_vector(7 downto 0);
begin
-- Obliczenie dwukrotnosci wyniku wejsciowego
-- w zaleznosci od sygnalu multiplier - bedzie wykorzystany lub nie
	mul2(7) <= datain(6);
	mul2(6) <= datain(5);
	mul2(5) <= datain(4);
	mul2(4) <= datain(3) xor datain(7);	-- xorowanie z 11b, jezeli nasapilo przepelnienie
	mul2(3) <= datain(2) xor datain(7);	-- przy przesuwaniu bitowym
	mul2(2) <= datain(1);
	mul2(1) <= datain(0) xor datain(7);
	mul2(0) <= datain(7);	-- to jest "0 xor datain(7)" 

	-- W zaleznosci od wartosci multiplier - na wyjsciu jest 0,       datain,   datain<<1, lub datain xor datain<<1
	--                                          rownowaznie: 0*datain, 1*datain, 2*datain   lub 3*datain
	dataout(7) <= (datain(7) and multiplier(0)) xor (mul2(7) and multiplier(1));
	dataout(6) <= (datain(6) and multiplier(0)) xor (mul2(6) and multiplier(1));
	dataout(5) <= (datain(5) and multiplier(0)) xor (mul2(5) and multiplier(1));
	dataout(4) <= (datain(4) and multiplier(0)) xor (mul2(4) and multiplier(1));
	dataout(3) <= (datain(3) and multiplier(0)) xor (mul2(3) and multiplier(1));
	dataout(2) <= (datain(2) and multiplier(0)) xor (mul2(2) and multiplier(1));
	dataout(1) <= (datain(1) and multiplier(0)) xor (mul2(1) and multiplier(1));
	dataout(0) <= (datain(0) and multiplier(0)) xor (mul2(0) and multiplier(1));
end Behavioral;
